تصميم الذاكرة الرئيسية

Main memory/Part2
By Noor Kadhum
Architecture For 3rd Stage
Computer Science

Decders and multi chips
The connection of memory chipd to the cpu is shown in the following figure.this configuration gives a memry capacity of 512 bytes of RAM and 512 bytes of ROM the selection between RAM and ROM is achieved by CS2 bit. RAM has 4 chips the question is : How the computer knows the required chip?
This done by 2×4 decoder whose outputs go to CS1 inputsin each RAM chip:
CS1 Selected chip
0 0 RAM1
0 1 RAM2
1 0 RAM3
1 1 RAM4

Note that RD an WR utputs from CPU are applied to the inputs of each RAM chip.ROM chip is connected with RD only.

Memory connection t CPU

Exercise:
Draw the address format for ROM consists of 1 chip and the selected address is the third one.
Example: designing Main Memory:
Desingnate a M.M of 1KB consisting of chips of 128 byte (RAM) and single chip for ROM.
SOL:
a- Devide M.M size into two halves equally between RAM and ROM.
1KB= 210 B
Size of ROM= Size of RAM = 210/2 = 29= 512 byte
b- Compute the NO.of each chip :

the no. of chip (RAM) = size of RAM/size of CHIP
= 29/27=22=4 chips
The no. of chip(ROM) =1 (given) .
M.M consists 5 chips as a whole [ 4chips (RAM)+1chip (ROM)], and they are connected to the CPU in the same way explained previously.
Exercises
A-Suppose that :
- RAM consists of 8 chips with 128 byte for each.
- ROM consists of 2 chips,what is the size of each chip?
- Find the size of main memory based on your answers of the previous points.
B-The size of M.M=1MB. The size of RAM chip is equal to the size of ROM chip and equal to 1 KB. find the no. of bits in each field in the address.
Next Lecture
The next clamshell we will learn about another kind of memories , the cache. See you next week, God willing,