L8:Computer Architecture

7- 3 CPU Instruction Cycle
The basic actions during fetching an instruction, executing an instruction, or
handling an interrupt are defined by a sequence of micro-operations. A group of
control signals must be enabled in a prescribed sequence to trigger the execution of
a micro-operation.
In this section, we study the micro-operations that implement instruction
fetch, execution of simple arithmetic instructions (Sequential and Branch).
Fetch Instructions:
The sequence of events in fetching an instruction can be summarized as
follows:
The contents of the PC are loaded into the MAR to be the current address. The
value in the PC is incremented. (This operation can be done in parallel with a
memory access.) As a result of a memory read operation, the instruction is loaded
into the MDR. The contents of the MDR are loaded into the IR.
The micro-operations of instruction fetch take the following sequence:
1- Pc out ,ARin,Read,Set carry of ALU, Clear y,Add, Zin.
2-Zout, Pcin, WMFC (Wait for Memory-Function-Completed signal).
3- DRout,IRin .