Lecture_18_ Advanced Processor Design

9 Advanced Processor Design

9.1 Pipelined Processors

9.1.1 Basic Concept
The key thing to grasp when considering pipelined processors is that we can have more than one instruction in-flight at a time: this is the concept of ILP being put to practical use. To see why this might be the case, consider Table 9.1 which details an execution timeline for our original sequential data-path. In cycle t0 we fetch instruction #0 which is then decoded in cycle t1, executed in cycle t2 and finally writes results in cycle t3; we then fetch instruction #1 in cycle t4 and so on. Now imagine we split the sequential data-path into four pipeline stages, one each for fetch, decode, execute and write. A conceptual diagram of how this would look, which is used as a standard starting point for further discussion, is shown in
Figure 39. With such a design the fetch stage, for example, can be fetching instruction #2 while the decode stage is dealing with instruction #1 and the execute stage is dealing with instruction #0 and so on. This is highlighted in Table 9.2. With all stages working in parallel with each other, we execute around four times as many instructions in the same period; clearly this depends on factors previously introduced such as the requirement to keep the pipeline full and further complications we will introduce later.
To make this scheme possible we need to design a pipelined data-path which is capable of splitting the original into stages, each of which can operate independently on a different instruction. Figure 40 describes the “classic” way to do this; the design is composed of five stages in total: the fetch, decode, execute and write already described, together with a dedicated memory access stage. There are several ways this basic design can be improved but it offers a good, simple starting point. For brevity, we denote these stages FET, DEC, EXE, MEM and WRI. In the diagram, notice that the stages are separated by pipeline registers just like in our basic pipelined circuit; we denote these registers FET ?DEC, DEC ?EXE, EXE ?MEM and MEM ?WRI. The registers hold several different values even though we have drawn them as a single block. When we need to, we subscript the pipeline register with the conventional register name from the sequential data-path. So for example FET ?DECPC is the value of the program counter register held in pipeline FET?DEC, the value of the instruction register at DEC?EXE is DEC?EXEIR.