RISC and CISC Designs

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risc and cisc designs
the two basic types of processor design philosophies: reduced instruction set computers (risc) and complex instruction set computers (cisc). first, let us talk about the trend line. the current trend in processor design is to use risc philosophy. in the 1970s and early 1980s, processors followed the cisc designs. to understand this shift from cisc to risc, we need to look at the motivation for going the cisc way initially. but first we have to explain what these two types of design philosophies are.
for example, adding two integers is considered a simple instruction. but, an instruction that copies an element from one array to another and automatically updatings both array subscripts is considered a complex instruction. risc systems use only simple instructions such as the addition. furthermore, risc systems assume that the required operands are in the processor’s registers, not in main memory. a cisc processor does not impose such restrictions. so what? it turn`s out that characteristics like simple instructions and restrictions like register-based operands not only simplify the processor design but also result in a processor that provides improved application performance.
how come the early designers did not think about the risc way of designing processors? several factors contributed to the popularity of cisc in the 1970s. in those days, memory was very expensive and small in capacity. for example, even in the mid-1970s, the price of a small 16 kb memory was about $500. you can imagine the cost of memory in the 1950s and 1960s. so there was a need to minimize the amount of memory required to store a program. an implication of this requirement is that each processor instruction must do more, leading to complex instructions. this caused another problem. how can a processor be designed that can execute such complex instructions using the technology of the day? complex instructions meant complex hardware, which was also expensive. this was a problem processor designers grappled with until wilkes proposed microprogrammed control in 1951.
a microprogram is a small run-time interpreter that takes the complex instruction and generates a sequence of simple instructions that can be executed by hardware. thus the hardware need not be complex. once it became possible to design such complex processors by using microprogrammed control, designers went crazy and tried to close the semantic gap between the instructions of the processor and high-level languages. this semantic gap refers to the fact that each instruction in a high-level language specifies a lot more work than an instruction in the machine language. think of a while loop statement in a high-level language such as c, for example. if we have a processor instruction with the while loop semantics, we could just use one machine language instruction. thus, most cisc designs use microprogrammed control, as shown in figure 19.












risc designs, on the other hand, eliminate the microprogram layer and use the hardware to directly execute instructions. here is another reason why risc processors can potentially give improved performance. one advantage of using microprogrammed control is that we can implement variations on the basic isa architecture by simply modifying the microprogram there is no need to change the underlying hardware, as shown in figure 20. thus, it is possible to come up with cheaper versions as well as high-performance processors for the same family.



















the pentium processor, belongs to what is known as the complex instruction set computer (cisc) design. the obvious reason for this classification is the “complex” nature of its instruction set architecture (isa). it is sufficient to know that the pentium isa provides a lot of support for higher-level languages (hlls) at the expense of increased instruction set complexity. two examples of complexity are the large number of addressing modes provided and wide range of operations—from simple to complex—supported. the motivation for designing such a complex instruction set is to provide an instruction set that closely supports the operations and data structures used by hlls.
the decision of cisc processor designers to provide a variety of addressing modes leads to variable-length instructions. for example, instruction length increases if an operand is in memory as opposed to in a register. this is because we have to specify the memory address as part of instruction encoding, which takes many more bits. as we show later, this complicates instruction decoding and scheduling. the side effect of providing a wide range of instruction types is that the number of clocks required to execute instructions also varies widely. this again leads to problems in instruction scheduling and pipelining.
for these and other reasons, in the early 1980s designers started looking at simple isas.
since these isas tend to produce instruction sets with far fewer instructions, they coined the
term reduced instruction set computer (risc). even though the main goal was not to reduce the number of instructions, but the complexity.